Universal Asynchronous Receiver/Transmitter
The parallel side of a UART is usually connected to the bus of a computer. When the computer writes a byte to the UART's transmit data register (TDR), the UART will start to transmit it on the serial line. The UART's status register contains a flag bit which the computer can read to see if the UART is ready to transmit another byte. Another status register bit says whether the UART has received a byte from the serial line, in which case the computer should read it from the receive data register (RDR). If another byte is received before the previous one is read, the UART will signal an "overrun" error via another status bit.
The UART's serial connections usually go via separate line driver and line receiver integrated circuits which provide the power and voltages required to drive the serial line and give some protection against noise on the line.
Data on the serial line is formatted by the UART according to the setting of the UART's control register. This may also determine the transmit and receive baud rates if the UART contains its own clock circuits or "baud rate generators". If incorrectly formated data is received the UART may signal a "framing error" or "parity error".
Often the clock will run at 16 times the baud rate (bits per second) to allow the receiver to do centre sampling - i.e. to read each bit in the middle of its allotted time period. This makes the UART more tolerant to variations in the clock rate ("jitter") of the incoming data.
An example of a late 1980s UART was the Intel 8450. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. For example, the Intel 16550 has a 16 byte FIFO. Variants include the 16C550, 16C650, 16C750, and 16C850.
See also bit bang.